The present invention relates to the formation of semiconductor devices. More specifically, the invention relates to the etching of high aspect ratio features for semiconductor devices.
During semiconductor wafer processing, 3D flash memory devices may be created using multiple cells, which are stacked up together in chain format to save space and increase packing density. One common arrangement is an ONON structure, which includes alternating layers of Silicon Oxide (the “O”) and Silicon Nitride (the “N”). These stacks may be etched to produce features as part of methods for making 3D structures such as NAND flash memory chips.